Error (10327):VHDL error at xd.vhd(17):can't determine defin

来源：学生作业帮编辑：作业帮分类：综合作业时间：2024/05/11 15:59:06

Error (10327):VHDL error at xd.vhd(17):can't determine definition of operator ""+"" -- found 0 pos
初学VHDL~
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xd IS
PORT (sel :IN std_logic;
d0,d1 :IN std_logic;
led :OUT std_logic);
END ENTITY xd;
ARCHITECTURE abc OF xd IS
signal num0 :std_logic_VECTOR(7 DOWNTO 0);
signal num :std_logic_VECTOR(7 DOWNTO 0);
BEGIN
num0

第二行添加
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

Error (10327):VHDL error at xd.vhd(17):can't determine defin Error (10327):VHDL error at Vhdl1.vhd(16):can't determine de vhdl VHDL error at dt.vhd(25):can't determine definition of Error (10482): VHDL error at MUX4_1.vhd(18): object "STD_LOG Error (10500): VHDL syntax error at cj200.vhd(17) near text VHDL程序错误 Error (10482):VHDL error at washtop.vhd(33):object Error (10500):VHDL syntax error at bijiao.vhd(26) near text Error (10500):VHDL syntax error at cqg.vhd(31) near text ":= Error (10500):VHDL syntax error at biaojue.vhd(16) near text quartusII 运行报错（1）Error (10500):VHDL syntax error at vga.vhd( Error (10334):VHDL error at frame.vhd(6):entity "frame" is u Error (10818):vhdl