USE IEEE.STD_LOGIC_UNSIGNED.ALL; 报错
来源:学生作业帮 编辑:作业帮 分类:综合作业 时间:2024/05/13 06:32:45
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 报错
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT (CLK,RST,EN,LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END CNT10;
ARCHITECTURE behav OF CNT10 IS
BEGIN
PROCESS(CLK,RST,EN,LOAD)
VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='0' THEN Q:=(OTHERS=>'0');
ELSIF CLK' EVENT AND CLK='1' THEN
IF EN='1' THEN
IF (LOAD='0') THEN Q:=DATA;ELSE
IF Q'0');
ENDIF;
ENDIF;
ENDIF;
ENDIF;
IF Q="1001" THEN COUT
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT (CLK,RST,EN,LOAD:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END CNT10;
ARCHITECTURE behav OF CNT10 IS
BEGIN
PROCESS(CLK,RST,EN,LOAD)
VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='0' THEN Q:=(OTHERS=>'0');
ELSIF CLK' EVENT AND CLK='1' THEN
IF EN='1' THEN
IF (LOAD='0') THEN Q:=DATA;ELSE
IF Q'0');
ENDIF;
ENDIF;
ENDIF;
ENDIF;
IF Q="1001" THEN COUT
第二行少了个分号,后面连续的四个end if中间是有空格的~
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 报错
USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all
fen100 library ieee; use ieee.std_logic_1164.all; use ieee.s
MAXPLUS2中,USE IEEE.STD_LOGIC_ARITH.ALL和USE IEEE.STD_LOGIC_UN
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUXK IS PO
1、vhdl中,USE IEEE.NUMERIC_STD.ALL;这个文件的作用是什么?
USE IEEE.STD_LOGIC_ARITH.用来干嘛的
EDA中IEEE.STD_LOGIC_ARITH.ALL是什么呢?
eda中vhdl 开头的LIBRARY ieee和USE ieee.std_logic_1164.
Pease Use all the points
LIBRARY IEEE;
报错c(179) :error C2275:'LNODE' :illegal use of this type as a