作业帮请英语高手帮忙翻译一下,有赏分,谢谢!
来源：学生作业帮 编辑：作业帮 分类：英语作业 时间：2024/05/14 14:54:40
请英语高手帮忙翻译一下,有赏分,谢谢!
PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
o Spread Spectrum Clock Isolation
- Dual clock domain
o Quality of Service (QoS)
- Two Virtual Channels (VC) per port
- Eight Traffic Classes per port
- Weighted Round-Robin Port & VC
Arbitration
o Reliability, Availability, Serviceability
- All ports Hot-Plug capable thru I2C
(Hot-Plug Controller on every port)
- ECRC & Poison bit support
- Data path protection
- Memory (RAM) error correction
- Advanced Error Reporting support
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance monitoring
(per port payload & header counters)
- JTAG AC/DC boundary scan
- Fatal Error (FATAL_ERR#) output signal
- INTA# output signal
The ExpressLane™ PEX 8604 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including control plane applications, consumer applications and embedded systems. The PEX 8604 is well suited for fan-out,
peer-to-peer, and intelligent I/O module applications.
Low Packet Latency & High Performance
The PEX 8604 architecture supports packet cut-thru with a maximum latency of 190ns in x1 to x1 configuration. This, combined with low power consumption and non-blocking internal switch architecture, provides full line rate on all ports for lowpower applications such as consumer and embedded. The low latency enables applications to achieve high throughput and performance. In addition to low latency,
the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout.
Data Integrity
The PEX 8604 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory (RAM) error correction as packets pass through the
switch.
Dual-Host and Fail-Over Support
The PEX 8604 supports full non-transparent bridging (NTB) functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as select embedded applications.Non-transparent bridges allow systems to isolate host memory domains by
presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses, doorbell registers are used to send interrupts between the address domains, and scratchpad registers are accessible from both address domains to allow inter-processor communication.Interoperability
All PLX switches undergo thorough interoperability testing in PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure compatibility with PCI Express devices in the market.
PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
o Spread Spectrum Clock Isolation
- Dual clock domain
o Quality of Service (QoS)
- Two Virtual Channels (VC) per port
- Eight Traffic Classes per port
- Weighted Round-Robin Port & VC
Arbitration
o Reliability, Availability, Serviceability
- All ports Hot-Plug capable thru I2C
(Hot-Plug Controller on every port)
- ECRC & Poison bit support
- Data path protection
- Memory (RAM) error correction
- Advanced Error Reporting support
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance monitoring
(per port payload & header counters)
- JTAG AC/DC boundary scan
- Fatal Error (FATAL_ERR#) output signal
- INTA# output signal
The ExpressLane™ PEX 8604 device offers PCI Express switching capability enabling users to add scalable high bandwidth non-blocking interconnection to a wide variety of applications including control plane applications, consumer applications and embedded systems. The PEX 8604 is well suited for fan-out,
peer-to-peer, and intelligent I/O module applications.
Low Packet Latency & High Performance
The PEX 8604 architecture supports packet cut-thru with a maximum latency of 190ns in x1 to x1 configuration. This, combined with low power consumption and non-blocking internal switch architecture, provides full line rate on all ports for lowpower applications such as consumer and embedded. The low latency enables applications to achieve high throughput and performance. In addition to low latency,
the device supports a max payload size of 2048 bytes, enabling the user to achieve even higher throughout.
Data Integrity
The PEX 8604 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory (RAM) error correction as packets pass through the
switch.
Dual-Host and Fail-Over Support
The PEX 8604 supports full non-transparent bridging (NTB) functionality to allow implementation of multi-host systems and intelligent I/O modules in applications which require redundancy support such as select embedded applications.Non-transparent bridges allow systems to isolate host memory domains by
presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses, doorbell registers are used to send interrupts between the address domains, and scratchpad registers are accessible from both address domains to allow inter-processor communication.Interoperability
All PLX switches undergo thorough interoperability testing in PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure compatibility with PCI Express devices in the market.
PCI明确力量管理 -链接力量管理状态：L0,L0s,L1,L2/L3准备和L3 -设备状态：D0和D3hot o扩展视谱时钟隔离 -双重时钟领域 o服务质量(QoS) -二条虚拟通道(VC)每个口岸 -每个口岸八交通类 -被衡量的联名声明港& VC 仲裁 o可靠性,可及性,操作性能 -所有口岸热插座可胜任的通过I2C (在每个口岸的热插座控制器) - ECRC & 毒物位支持 -数据通路保护 -错误校正的记忆(RAM) -先进的错误报告支持 -端口状况可利用的位和的GPIO -每港错误诊断 -性能监测 (每港酬载& 倒栽跳水柜台) - JTAG AC/DC界限扫瞄 -致命错误(FATAL_ERR#)输出信号 - INTA#输出信号 ExpressLane™ PEX 8604设备提议PCI明确开关能力使用户增加可升级的高带宽非阻塞互联到各种各样的应用包括控制飞机应用、消费者应用和嵌入系统.PEX 8604为输出端是非常合适的,对等和聪明的输入/输出模块应用.低小包潜伏& 高性能 切开通过与190ns最大潜伏的PEX 8604建筑学支持小包在x1的对x1配置.这,与低功率消耗量和非阻塞内部开关建筑学结合,在所有口岸提供轮廓鲜明的率为低功率应用例如消费者并且埋置了.低潜伏使应用完成高生产量和表现.除低潜伏之外,设备支持2048个字节的最大酬载大小,使用户更高始终达到.数据完整性 PEX 8604提供端到端CRC保护(ECRC)和毒物位支持使能要求保证的无错的小包的设计.PLX也支持数据通路错误校正的同等和的记忆(RAM),当小包穿过 开关.双重主人和故障转移支持 PEX 8604支持充分的不透明的跨接的(NTB)功能允许多主人系统和在要求多余支持例如精选的嵌入应用的应用的聪明的输入/输出模块的实施.不透明的桥梁允许系统隔绝主人记忆领域 提出处理器子系统作为终点而不是另一个存储系统.基地址寄存器被用于翻译地址,门铃记数器被用于送中断在地址领域之间,并且高速暂存的记数器从两个地址领域是容易接近的允许相互处理器通信.互用性 所有PLX开关接受在PLX的互用性实验室和服从测试的周到互用性测试在PCI-SIG插座fest保证与PCI明确设备的兼容性在市场上.