电机驱动芯片SA57U的英文说明PDF的翻译

电机驱动芯片SA57U的英文说明PDF的翻译
VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency
characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS
and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and
potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding
bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply
current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B & C supply pins
(46-49) are monitored for undervoltage conditions.
OUT 1 , OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each
pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of
this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands,
this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resistor.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower Nchannel
output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry
will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the
top and bottom input signals.
1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper Pchannel
FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel FET off.
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VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B & C supply pins (46-49) are monitored for undervoltage conditions.
VS：输出晶体管的供电电压.这些引脚需要解耦（推荐采用具有良好高频特性的1μF电容器）到PGND（电源接地）引脚.该解耦电容器应该定位在尽可能接近VS和PGND的地方.在VS引脚处需要额外的电容来处理负载电流的峰值和电位电机的再生.参见本数据表的应用（applications）小节,关于旁路电容器选择的额外讨论.请注意,VS引脚29－31只承载相位1的电源电流.引脚46－49承载相位2的电源电留.相位1可以在与相位2不同的电源电压下工作.只有B和C电源引脚（46－49）被监控欠压条件.
OUT 1 , OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
OUT1,OUT2（输出1,输出2）：这些引脚是功率输出与负载的连接.请注意：当驱动一个感性负载时,我们建议,将两个具有良好切换特性（快速反向回复时间规格）肖特基二极管链接到每一个引脚,从而使它们与输出场效应晶体管的寄生背体二极管并联（见2.6小节）.
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details.
PGND：电源接地.这是用于输出场效应晶体管（FET）的大地回线连接.来自负载的回流电流流过这些引脚.PGND通过一个及欧姆的电阻内部连接到SGND.参见本数据表的2.1小节了解更多细节.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resistor.
SC：短路输出.如果在任何不符合输入指令的输出上检测到一个状态,这就表明一个短路的状态,而且SC引脚走高.在切换过渡期间,SC信号就被消失约200ns,但是在大电流应用中,在SC引脚上可能出现短的假信号.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower Nchannel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals.
1b,2b：这两个施密特触发的逻辑电平输入负责将相关的底部或下方N沟道FET开通或切断. 逻辑高接通底部N沟道FET, 而逻辑低则切断下侧N沟道FET.如果1b或2b同时高,那相当于1t或2t的输入高,那么两个FET的保护电路将切断,以便防止在该输出相的直通电流.保护电路还包括一个死区时间发生器,它在顶部和底部输入信号同时切换情况下,在输出中插入死区时间.
1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper Pchannel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel FET off.
1t,2t：这两个施密特触发的逻辑电平输入负责将相关的顶部或上方P沟道FET输出开通或切断. 逻辑高接通顶部P沟道FET, 而逻辑低则切断顶部P沟道FET.